A phase lock loop (PLL) circuit is a circuit that is used for the synchronization of signals. Phase lock loops are used in a wide variety of electronic circuits where signals containing analog and digital information are decoded. They may be used in optical tachometers, motor control, television receivers, disk drives, modems, radios, and many other fields. Their use within the communications field is extensive.
Phase lock loops may be thought of as synchronizing circuits in which an output frequency is synchronized or locked to a reference frequency.
Some of the most commonly familiar uses of phase lock loops occur within a television receiver. When a signal is sent from a broadcast station to the television receiver the signal must be decoded to represent a picture and sound to be displayed on the television receiver. The television receiver must synchronize the portion of the picture being broadcast that represents the top of the picture to the top of the television screen, the television receiver must also synchronize the portion of the picture being broadcast that represents the left side of the picture to the left side of the television screen. The television receiver must also synchronize the colors received in the signal to the colors displayed on the television, so that the red remains red, the blue remains blue, and all the colors match those being broadcast. Somewhat less apparent is the fact that the television must synchronize itself to the sound carrier signal within the television signal so that the sound associated with the picture may be properly demodulated and reproduced through the speakers. All of these synchronizations typically occur through the use of phase lock loops in which the signals which are broadcast from the television transmitter are synchronized to the television circuits which actually display these signals.
PLLs are also used in mobile communication applications related to such purposes as frequency generation, signal modulation and demodulation, and data decoding and encoding.
PLLs are unsynchronized when they power on or have no reference signal. In this condition the PLLs are said to be unlocked or out of lock. Phase lock loops generally work by comparing a reference frequency to a generated output frequency and adjusting the output frequency to match the reference frequency. As the output signal is adjusted by the loop there occurs a point at which the frequencies of the output and reference signals match. At this point the signals are sometimes said to be in frequency lock. When the generated frequency is further synchronized in phase with the input frequency the condition is often referred to as phase lock, the locked state, or simply lock. During lock, when the output frequency is synchronized with the reference frequency, the phase error between these signals may be very small or even zero. In the lock state the output signal will generally stay in lock until the phase lock loop is somehow perturbed. Some common factors that perturb phase lock loops are loss of the reference frequency, a change in the frequency or phase of the reference frequency, noise on the reference frequency, or noise in the system which disturbs the loop.
There are large number of variations of phase lock loops, and a large number of possible classifications, but they can be grouped into phase lock loops which contain only analog components, and phase lock loops that contain some or all digital components. The common analog or linear phase lock loops were the first to be developed. These phase lock loops ordinarily consist of three parts: 1) the phase detector, which compares the incoming reference frequency to the output frequency, 2) the loop filter, which is typically a low pass type filter built form an active or passive RC filter, and 3) a voltage controlled oscillator. Digital elements have been gradually integrated into PLLs and hybrid versions have emerged which contain both analog and digital functions. All digital phase lock loop versions have also emerged in which all of the circuit functions are performed by digital circuits. With the advent of cheap fast microcontrollers software versions of the phase lock loop, in which the loop functions are performed by a high speed microprocessor or microcontroller, have been developed. All of the different varieties of phase lock loops find use in modern electronics, with the digital versions achieving increasing popularity as their costs drop and their level of integration increases.
The various versions of phase lock loops behave differently and there is no universal theory that covers all versions of PLLs. There is also a great deal of variation in implementation details as phase lock loops are commonly tailored to the many applications that they serve. Because of the great variations, phase lock loops do not completely lend themselves to hard and fast rules defining classifications. The different types of phase lock loops, fortunately, have many parts in common and many of the principles that apply to one apply to the others.
An example of an analog or linear phase lock loop is shown in FIG. 1. A reference frequency signal 103, is provided to a phase detector 105, where it is compared with the output frequency signal 115. The phase detector 105, compares the phases of the two signals and produces an output 107 that is proportional to the phase difference between the signals. The output of the phase detector 107 is then coupled to a loop filter 109, which determines the frequency response, and produces an output signal 111. The output of the loop filter 111 is coupled to a voltage controlled oscillator 113 which maintains the same frequency if the loop was locked, that if the output frequency signal and the reference frequency signal were in phase. If the output frequency signal and the reference frequency signal are not in phase the output of the loop filter 111 will be such as to adjust the frequency of the voltage controlled oscillator 113 in order to bring the circuit into lock.
The phase lock loop has found extensive use in mobile communication circuits such as portable telephones. They are used to lock to transmitting and receiving frequencies and to recover clock signals from different digital data formats such as return to zero (RZ) and non return to zero (NRZ). As the communications devices, particularly portable telephones, have grown smaller and smaller the desire to obtain more operating time out of smaller and smaller packages has increased. Both small size and long battery life, which can be somewhat opposite constraints, are typically seen as desirable characteristics.
There are two ways to address the desire to have smaller portable communications devices with increased operational time. The first is to produce more powerfill batteries with a higher energy density and the second is to produce circuitry that consumes less power.
Several approaches are in use to minimize the rate of power consumption by these portable devices. One approach is to minimize the voltage on the circuitry within these portable devices by using circuit components that can operate at lower voltages. Another approach to minimize power consumption is to adopt techniques to enable operation of circuitry within the portable units only part of the time instead of continuously. For example the TDMA (Time Division Multiple Access) protocol, which allows several portable phones to share the same frequency by broadcasting only part of the time in successive time slots. By broadcasting during a time slot instead of continuously, the output power amplifier can be shut off for most of the time that the phone is active and the power is conserved.